There is a trend towards the reduction of supply voltage levels in integrated circuits, especially to reduce their electrical power consumption. This forces integrated circuit designers to develop appropriate technologies to reduce the levels of the threshold voltages of transistors for these transistors to operate in a sufficiently reliable manner at a lower supply voltage. This is done while maintaining or even improving the speed of operation. However, the technology used imposes limits. In one example, reference is made to 0.25 micron CMOS technology. To obtain low threshold voltages for the transistors, the nominal values .vertline.Vtp.vertline.=475 millivolts for a P-type transistor and Vtn=469 microvolts for an N-type transistor, require a total voltage of about 900 millivolts. Accordingly, there is some difficulty in operating such a device at a logic supply voltage of 1 volt or less using 0.25 micron technology.
One way of operating an integrated circuit at a low voltage or a very low voltage is to modify the characteristics of certain transistors on critical conduction paths. For this purpose, a negative voltage can be applied where a zero voltage is commonly used. In the invention, it is sought, more particularly, to switch over the zero voltages using P-type MOS transistors connected to a load line. A load line, for example, is connected to a row of dynamic memory cells.
In an example of this kind, to store a 0 in the row, a row decoder commonly switches to ground Gnd. As a first approximation, and overlooking the substrate effect, the level Gnd - Vtp is present on the row. In practice, several hundreds of millivolts are measured. If the supply voltage decreases, the operating window of the read circuit becomes too small. The period of retention in the memory thus becomes greatly reduced. The switching needs to be carried out using the most negative possible voltage. The negative voltage must be within the limit of voltages that are acceptable and compatible with known standards for achieving reliable components for the technologies used. As a result, the window of operation would be widened.
In one example using a dynamic memory, the negative voltage is to be applied to a large load, such as the row of memory cells. A negative load pump device is therefore used to provide a negative voltage at output. There are known negative load pump devices used in combination with row decoders. U.S. Pat. No. 5,168,174 describes a device of this kind. However, there are high negative voltage levels, e.g., in the range of -11 volts, used for the electrical erasure of non-volatile memories. However, these operating devices do not work at low voltages.